Memory devices include storage locations for configuration information to set optional or configurable operations of the memory device. The storage locations can be referred to as configuration registers, and are frequently referred to as mode registers. The different configurations can change the operational mode of the memory device. Configurable operation of the memory device can include settings related to speed of communication, timing settings, termination settings, or others, or a combination.
Traditionally mode registers are located in close proximity to each other, and have similar read and write times. Typically mode registers are read and written by the same data bus used to access the memory array of user data. When a mode register is placed in a different location, additional logic circuits may be required to ensure that the read or write times or both are the same or within a range of read and write times for mode registers. The additional logic circuitry results in increased design and implementation costs. Reducing the amount of logic can result in a mode register that has different read and write times. For example, implementing logic to enable the writing or configuring of the mode registers within expected timings, but not implementing the logic to enable the reading of the mode registers within expected timings can result in a memory device with a mode register that has a read time slower than the write time. Differences in read and write timing can complicate the access to the mode register.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.